The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor memory device which operates in synchronism with a clock signal.
As processing speed of CPUs is enhanced, semiconductor memory devices such as a DRAM (dynamic random access memory) are required to have an increased data-transfer speed by using an increased signal frequency for input/output of data signals. SDRAMs (synchronous dynamic random access memory) are devised to meet this demand, and operate in synchronism with an input clock signal to achieve a high-operation speed.
FIG. 1 is a circuit diagram showing a portion of a DRAM with regard to peripherals of memory cells. The circuit of FIG. 1 includes a capacitor 501, NMOS transistors 502 through 512, a PMOS transistor 513, PMOS transistors 521 and 522, and NMOS transistors 523 and 524. The PMOS transistors 521 and 522 and the NMOS transistors 523 and 524 together form a sense amplifier 520.
The capacitor 501 serving as a memory cell stores 1-bit information. When a sub-word-line selecting signal SW is activated, the NMOS transistor 502 serving as a cell gate opens, thereby transferring data of the capacitor 501 to a bit-line BL. When this happens, a bit-line-transfer signal BLT1 is at a HIGH level, so that the NMOS transistors 503 and 504 are turned on. A bit-line-transfer signal BLT0, on the other hand, is at a LOW level, so that the NMOS transistors 505 and 506 are turned off. As a result, the data on the bit-lines BL and /BL is stored in the sense amplifier 520 via the NMOS transistors 503 and 504. The sense amplifier 520 operates when the transistors 513 and 512 are turned on via activation of sense-amplifier-activation signals SA1 and SA2, and amplifies the data of the bit-lines BL and /BL. The amplified data on the bit-lines BL and /BL is then sent to data bus DB and /DB via the NMOS transistors 510 and 511 serving as column gates when a column-line selecting signal CL is selectively activated.
In the case of data-write operations, data on the data bus DB and /DB is stored in the capacitor 501 through operation steps reversed in order with reference to the case of data-read operations.
FIG. 2 is timing charts for explaining data-read operations of the DRAM.
As shown in FIG. 2, when data-read operations are conducted, commands are input to the DRAM in an order of a precharge command (PRE) for precharging the bit-lines BL and /BL to a predetermined voltage level, a /RAS command (R) for a row-access operation, and a /CAS command (C) for a column-access operation.
With reference to FIG. 1 and FIG. 2, timing control will be described below with regard to data-read operations.
Upon input of the /RAS command, the bit-line-transfer signal BLT0 becomes LOW (BLT1 is HIGH), so that the bit-lines BL and /BL are connected to the sense amplifier 520. At the same time, a precharge signal PR of FIG. 1 is changed to LOW to end the reset conditions of the bit-lines BL and /BL. Further, a main-word-line selecting signal MW is changed to HIGH, and so is the sub-word-line selecting signal SW, thereby selecting a particular word line. This turns on the NMOS transistor 502, so that the data of the capacitor 501 is read to the bit-line BL. As shown in FIG. 2, the data appears on the bit-line BL at a timing when the main-word-line selecting signal MW and the sub-word-line selecting signal SW become HIGH.
In order to drive the sense amplifier 520, then, sense-amplifier driving signals SA1 and SA2 become active, thereby turning on the NMOS transistor 512 and the PMOS transistor 513. As shown in FIG. 2, activation of the sense amplifier 520 results in an increase in the amplitude of data signals on the bit-lines BL and /BL.
When the amplitude of data signals is stepped up, the column-line selecting signal CL becomes HIGH in response to the /CAS command so as to select a particular column. The NMOS transistors 510 and 511 (column gates) of the selected column are turned on, so that the data is released to the data bus DB and /DB. The data on the data bus DB and /DB is output from the DRAM as a data signal DQ, and, for example, a data-read operation for consecutive four bits is conducted.
When the precharge command is input, the precharge signal PR becomes HIGH at an appropriate timing, so that the NMOS transistors 507 through 509 are turned on to precharge the bit-lines BL and /BL to a voltage VPR. This operation resets the bit-lines BL and /BL as shown in FIG. 2, and, thus, the DRAM is prepared for a data-read operation of a next /RAS command.
The DRAM as described above can consecutively read data from different column addresses by successively selecting different columns, and this operation is applicable when data is consecutively read from the same row address (corresponding to the same word line). The sense amplifier 520 of FIG. 1 is provided with respect to each of a plurality of columns. The plurality of sense amplifiers 520 store data of different column addresses and the same row address. When these different column addresses are successively selected to read data from the sense amplifier 520, therefore, consecutive data-read operations can be achieved.
When there is a need to read data from a different row address (corresponding to a different word line), however, new data needs to be read from memory cells of this word line to the bit-lines BL and /BL. Further, in order to transfer the new data to the bit-lines BL and /BL, it is required to precharge the bit-lines BL and /BL in advance. Because of this, when data is to be read from a different row address after having read data from a given row address, successive data-read timings have a large time gap therebetween as shown in FIG. 2. In the example of FIG. 2, there is a gap as large as 10 clocks between successive data-read timings for different row addresses.
For the sake of explanation, a whole series of operations from the input of a row address to the output of data is divided into three steps. The first step includes command-decode operations and peripheral-circuit operations, and the second step is comprised of sense-amplifier operations. The third step relates to data-output operations. In order to achieve pipe-line operations with regard to row access, the operations of the first step are initially conducted with regard to a first row access. When the operations of the second step start with regard to the first row access, a second row access begins the operations of the first step. Further, when the first row access starts the operations of the third step, the operations of the second step are conducted with regard to the second row access, and, also, the operations of the first step should start with regard to a third row access. In this manner, row-access pipe-line operations can be achieved if the operations of the first, second, and third steps are performed in parallel with respect to different row accesses.
In conventional DRAMs, however, a burst length can be set to different lengths when a plurality of column addresses are consecutively read at the same row address. That is, the number of data pieces subjected to consecutive data-read operations is defined by a specified burst length, and a corresponding number of data pieces, as indicated by the specified burst length, are read from consecutive column addresses. In this case, an operation period of the sense-amplifier operations at the second step, i.e., a period during which the sense amplifiers are operating to allow accesses to be made to consecutive column addresses, is subject to a change, depending on a burst length which is determined by a mode setting.
Since the operation period of the second step is subject to a change dependent on a mode setting, it is impossible to carry out undisturbed pipe-line operations with regard to row accesses. Namely, when situations are viewed from the side of a memory controller, the memory controller is not allowed to supply the /RAS commands (or activation commands) successively at constant intervals. Further, there is a need to change input timings of precharge commands in accordance with burst lengths, which also makes it difficult to perform row-access pipe-line operations.
Accordingly, there is a need for a semiconductor memory device which achieves row-access pipe-line operations when different row addresses are accessed.
A semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and the plurality of sense-amplifiers.
In the semiconductor memory device described above, when a series of operations from row-address input to data output is divided into command-decode and peripheral-circuit operations of a first step, sense-amplifier operations of a second step, and data-output operations of a third step, the sense-amplifier operations of the second step have a constant operation period irrespective of a specified burst length. Since the data of the sense amplifiers is read in parallel by simultaneously opening a plurality of column gates, it is sufficient for the sense amplifiers to operate only for a constant time period. This allows the period of the sense-amplifier operations of the second step to be constant, thereby achieving undisturbed row-access pipe-line operations. If it is incumbent upon the user to determine the precharge timing from outside of the semiconductor memory device, arbitrary nature of the precharge timing works as one of the causes to disturb the pipe-line operations. The present invention, however, uses the internal precharge signal to initiate reset operations, so that such a cause of disturbance is eliminated. Further, the precharge operation can be conducted at an optimum timing immediately after the data is read from the sense amplifiers, thereby achieving high-speed data-read operations having a high performance limited only by the capacity of sense-amplifier operations.
Further, according to the present invention, the data-conversion unit outputs the serial data by selecting a predetermined number of bits from the plurality of bits of the parallel data in accordance with a burst-length signal. Because of this, undisturbed row-access pipe-line operations can be performed while allowing a data read operation to cope with different burst-length settings.
Moreover, according to the present invention, the plurality of bits of the parallel data are read from the sense amplifiers in response to a single row access, and are converted into serial data to be output to an exterior of the semiconductor memory device. This achieves continuous data outputting without any break.
In addition, according to the present invention, the semiconductor memory device receives a row-access command and a column-access command as a single packet. Accordingly, a reduction in a row-access time leads to a reduction in time intervals between input commands. The row-access command and the column-access command may be input at two consecutive clock pulses, for example.
Further, according to the present invention, the precharge-signal-generation unit resets the bit lines and the sense amplifiers by using the internal precharge signal immediately after the parallel data is read from the sense amplifiers. Such an automatic precharge immediately after data access to the sense amplifiers can reduce intervals between row accesses as much as possible.
Moreover, according to the present invention, the precharge-signal-generation unit uses a series of delay elements for delaying signals by the first delay-time period, and, thus, can be implemented via a simple circuit structure.
Further, according to the present invention, the sense amplifiers are grouped into a plurality of sense-amplifier blocks such that row-access operations are performed only with respect to a selected one of the sense-amplifier blocks. This makes it possible to reduce the number of sense amplifiers driven at the same time, thereby reducing the load on control signals used in the row-access operations. This increases signal switching speed, and achieves signal control of such a high speed as to be in commensurate with a reduction in time intervals between the row accesses.
Moreover, according to the present invention, the semiconductor memory device further includes word decoders corresponding to the respective sense-amplifier blocks, the word decoders connecting the memory cells to the bit lines only with respect to the selected one of the sense-amplifier blocks at a time of the row access. The word decoders provided for the respective sense-amplifier blocks makes it possible to reduce the load on word-selection signals used in the row-access operations. This increases signal switching speed, and achieves control of the word-selection signals at such a high speed as to be in commensurate with a reduction in time intervals between the row accesses.
Further, according to the present invention, bit-line-transfer-signal-generation units corresponding to the respective sense-amplifier blocks are provided, and connect the bit lines to the sense amplifiers only with respect to the selected one of the sense-amplifier blocks at a time of the row access. The bit-line-transfer-signal-generation units provided for the respective sense-amplifier blocks make it possible to reduce the load on bit-line-transfer signals used in the row-access operations. This increases signal switching speed, and achieves control of the bit-line-transfer signals at such a high speed as to be in commensurate with a reduction in time intervals between the row accesses.
Further, according to the present invention, sense-amplifier-driving-signal-generation units corresponding to the respective sense-amplifier blocks are provided, and activate the sense amplifiers only with respect to the selected one of the sense-amplifier blocks at a time of the row access. The sense-amplifier-driving-signal-generation units provided for the respective sense-amplifier blocks make it possible to reduce the load on sense-amplifier driving signals used in the row-access operations. This increases signal switching speed, and achieves control of the sense-amplifier driving signals at such a high speed as to be in commensurate with a reduction in time intervals between the row accesses.
Furthermore, according to the present invention, the semiconductor memory device further includes a plurality of banks, each of which includes the memory cells, the sense amplifiers, and the bit lines, wherein the sense amplifiers are grouped into the plurality of sense-amplifier blocks in each of the plurality of banks. In this manner, the semiconductor memory device of the present invention may be implemented as having a multiple-bank structure.
Also, according to the present invention, the semiconductor memory further includes bit-line-transfer-signal generation units each provided for a corresponding set of more than one sense-amplifier block. This configuration can reduce a chip size of the semiconductor memory device in comparison to when each sense-amplifier block is provided with a corresponding bit-line-transfer-signal generation unit.
Further, according to the present invention, a series of operations including emergence of the data of the memory cells on the bit lines, amplification of the data by the sense amplifiers, and a reset of the bit lines and the sense amplifiers is continuously repeated at constant cycles without any intervening break period. Therefore, a pipe-line operation is performed based on a configuration that is appropriate for row-access pipe-line operations. This makes it possible to conduct consecutive row-access operations at such a high speed as may be close to performance limits of the sense amplifiers.
Moreover, according to the present invention, a direct-sense-amplifier circuit is provided so as to be used in transferring the data from the sense amplifiers to a data bus via column gates. This configuration eliminates fluctuation of a bit-line voltage level at a time of read operations. Therefore, it is possible to bring forward the timing of a bit-line precharge and to make operation cycles shorter.
Furthermore, according to the present invention, a row-access command and a column-access command are received at the same timing defined by an externally supplied clock signal. Because of this, a time period from the row-access command to outputting of data can be kept constant even when the clock signal is lowered of its frequency.